
IDT82V3285A
WAN PLL
Programming Information
122
August 7, 2009
OUT5_FREQ_CNFG - Output Clock 5 Frequency Configuration
OUTPUT_INV2 - Output Clock 4 & 5 Invert Configuration
Address:71H
Type: Read / Write
Default Value: 00001000
Bit
Name
Description
7 - 4
OUT5_PATH_SEL[3:0]
These bits select an input to OUT5.
0000 ~ 0011: The output of T0 APLL. (default: 0000)
0100: The output of T0 DPLL 77.76 MHz path.
0101: The output of T0 DPLL 12E1/24T1/E3/T3 path.
0110: The output of T0 DPLL 16E1/16T1 path.
0111: The output of T0 DPLL GSM/OBSAI/16E1/16T1 path.
1000 ~ 1011: The output of T4 APLL.
1100: The output of T4 DPLL 77.76 MHz path.
1101: The output of T4 DPLL 12E1/24T1/E3/T3 path.
1110: The output of T4 DPLL 16E1/16T1 path.
1111: The output of T4 DPLL GSM/GPS/16E1/16T1 path.
3 - 0
OUT5_DIVIDER[3:0]
These bits select a division factor of the divider for OUT5.
The output frequency is determined by the division factor and the signal derived from T0/T4 DPLL or T0/T4 APLL output
(selected by the OUT5_PATH_SEL[3:0] bits (b7~4, 71H)). If the signal is derived from one of the T0/T4 DPLL outputs,
please refer to
Table 24 for the division factor selection. If the signal is derived from the T0/T4 APLL output, please refer to
Table 25 for the division factor selection.
Address:72H
Type: Read / Write
Default Value: 01000000
Bit
Name
Description
7 - 2
-
Reserved.
1OUT5_INV
This bit determines whether the output on OUT5 is inverted.
0: Not inverted. (default)
1: Inverted.
0OUT4_INV
This bit determines whether the output on OUT4 is inverted.
0: Not inverted. (default)
1: Inverted.
76543210
OUT5_PATH_S
EL3
OUT5_PATH_S
EL2
OUT5_PATH_S
EL1
OUT5_PATH_S
EL0
OUT5_DIVIDER
3
OUT5_DIVIDER
2
OUT5_DIVIDER
1
OUT5_DIVIDER
0
76543210
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OUT5_INV
OUT4_INV